The server room has long been the undisputed kingdom of x86. Intel Xeon and AMD EPYC processors have governed data centre infrastructure for decades, and for most operators, swapping them out has been unthinkable. But a new challenger is mounting a serious — and increasingly credible — campaign for the throne. RISC-V, the open-source instruction set architecture (ISA) born in a Berkeley lab, has graduated from embedded microcontrollers and academic curiosity to a genuine contender for enterprise and hyperscale computing workloads.

So, is RISC-V actually ready to replace x86 in the data centre? The honest answer is: not quite yet — but the gap is closing faster than many expected, and the trajectory is unmistakable. This post breaks down where RISC-V stands today, what's driving the momentum, where the real obstacles lie, and what IT leaders and infrastructure architects should be doing right now.

What Is RISC-V and Why Does It Matter for the Data Centre?

RISC-V (pronounced "risk-five") is an open-standard ISA released under a royalty-free licence. Unlike x86 — which is a closed ecosystem controlled by Intel and AMD —

RISC-V is royalty-free and open by design, while x86 remains a closed, Intel/AMD-controlled ecosystem.

That single difference has profound commercial and geopolitical implications.

In 2025, the RISC-V ISA is mature, toolchains are stable, and core capabilities are robust — and we're seeing a global ecosystem where businesses are not only adopting open cores, they're actively building products and creating entirely new markets around them.

For data centre operators, the appeal is straightforward:

RISC-V shifts the balance in a market traditionally monopolised by a small number of hardware vendors, enhancing user choice and preventing vendor lock-in. Building on the introduction of the RVA23 profile, the upcoming server SoC specification addresses data centre-specific challenges and overcomes known legacy restraints.

The State of RISC-V Hardware: Who's Building Server-Class Silicon?

The hardware landscape has changed dramatically in the past 18 months. A wave of serious, data centre-grade RISC-V silicon is either shipping or approaching production.

Tenstorrent and the Performance Parity Milestone

For years, the primary knock on RISC-V was raw single-threaded performance. That criticism has a much shorter shelf life today.

The release of the "Ascalon-X" core by Tenstorrent — the AI chip startup led by legendary architect Jim Keller — has silenced many sceptics. Benchmarks from late 2025 demonstrate that Ascalon-X achieves approximately 22 SPECint2006 per GHz, placing it in direct parity with AMD's Zen 5 and ARM's Neoverse V3. This milestone proves that RISC-V can handle the "brawny" out-of-order execution tasks required for modern data centres.

Ventana, Qualcomm, and the M&A Signal

Qualcomm has acquired chip designer Ventana Micro Systems, which develops server processors based on the RISC-V architecture. According to Qualcomm, the move underscores "its commitment to advancing the RISC-V standard and ecosystem."

When one of the world's most powerful semiconductor companies makes a strategic acquisition in RISC-V server silicon, it sends a clear message to the industry.

Ventana's Veyron V2 offers up to 192 cores and RVA23 profiles improving cross-implementation compatibility.

NextSilicon and the Road Ahead

Even newer entrants are pushing the envelope.

NextSilicon is working towards releasing 64-core and 128-core processors, with availability targeted for early 2028.

The chip features a 10-wide instruction issue pipeline, a 480-entry reorder buffer, and can retire up to 16 scalar instructions per cycle

— specifications that put it squarely in enterprise territory.

Andrea Gallo, chief executive of RISC-V International, described the architecture as significant for future computing demands, stating that "RISC-V is the most compelling architecture for the future of AI, data centre, and HPC workloads."

The Software Ecosystem: Progress and Persistent Gaps

Hardware alone doesn't win data centres — software does. And this is where RISC-V's journey most closely parallels the ARM server story of the 2010s.

Efforts to introduce new technologies and displace long-term incumbents are not initiatives that succeed in just a few quarters. These programmes take years to execute.

The good news is that the software ecosystem is accelerating rapidly.

Linux, Red Hat, and Ubuntu

In May 2025, Red Hat announced the release of a developer edition of Red Hat Enterprise Linux (RHEL) for use on SiFive's latest RISC-V developer board, the HiFive Premier P550, and made RISC-V source code available for the CentOS community.

Then in July 2025, NVIDIA announced it is porting CUDA to RISC-V, using the HiFive Premier P550 as the starting point for this work. While no timeline was shared for when the code will be available, the announcement has already generated significant interest.

Rivos and Canonical have also partnered to enhance RISC-V-readiness in Ubuntu for data centres, creating a streamlined and optimised Linux experience specifically designed for Rivos platforms — marking a significant step in making Ubuntu more enterprise-ready for AI and data analytics use cases.

The RVA23 Profile: A Critical Standardisation Moment

One of the most important developments for data centre adoption is the ratification of the RVA23 profile.

If you build for RVA23, you know your software will run across a wide range of compatible hardware

— exactly the kind of predictability enterprise IT teams demand before committing to a new architecture.

Where the Gaps Remain

Honesty matters here.

RISC-V debugging remains fragmented. The evolving Debug Specification and divergent vendor implementations result in incomplete support and reliance on software breakpoints due to immature hardware features, while integration between hardware and software tools is hindered by ecosystem fragmentation.

The software ecosystem maturity requires continuous effort to develop consistent standards, comprehensive debugging tools, and a wider range of optimised software support. While IP availability is growing, there's a need for a broader range of readily available, optimised IP blocks specifically for AI tasks, and significant investment is still required.

Market Growth: The Numbers Behind the Momentum

The data centre and HPC opportunity for RISC-V is enormous — and analysts are paying close attention.

The data centres and HPC segment is projected to grow at a CAGR of 33.1% through 2034.

RISC-V International forecasts adoption to grow at a compound annual growth rate of 40% in the coming years, with the instruction set architecture expected to be used inside 16 billion system-on-chips by 2030.

According to analysis from SHD Group, RISC-V is exceeding expectations, projecting that market penetration will grow from 2.5% in 2021 to 33.7% by 2031 — a more than tenfold increase in just ten years.

Crucially, RISC-V is also becoming the default for a class of workloads that is reshaping the entire data centre landscape.

There has been a sea change throughout 2025, and it's safe to say that almost every new AI accelerator project is using RISC-V.

That matters enormously, because as AI inference moves deeper into the data centre, the architecture underpinning the accelerators is increasingly RISC-V.

RISC-V vs x86: An Honest Comparison

Let's address the core question directly.

In mid-2025, x86 remains the top performer for legacy software and high-end workloads, with 64-core or 96-core Xeon/EPYC-class servers still setting the benchmark.

That dominance is real and shouldn't be minimised.

Where RISC-V wins today:

Beyond standard extensions, RISC-V supports the creation of custom extensions, meaning chip designers can add specialised instructions for cryptography, signal processing, or AI workloads

— something impossible within the x86 closed ISA.
- Cost structure:

Unlike ARM and x86, RISC-V does not require licensing fees, which reduces costs.

At hyperscale volumes, this matters enormously for total cost of ownership.
- AI acceleration:

RISC-V's dual advantage of standardisation and customisation makes it ideal for domain-specific compute. With RISC-V's modular ISA, designers can tightly integrate neural processing units to accelerate inference, cut energy use, and boost real-time AI responsiveness.

By diversifying access to constrained inventories, RISC-V levels the playing field for operators of all sizes and budgets, and fosters autonomy, empowering operators to evolve their technology stack without reliance on a select few vendors.

Where x86 still wins:

The realistic near-term picture is not full replacement, but strategic deployment — using RISC-V for workloads where its customisability, cost, and AI-native architecture offer clear advantages, while x86 continues to serve legacy and general-purpose compute.

Practical Tips: How to Start Evaluating RISC-V for Your Data Centre

You don't need to rip out your Xeon fleet tomorrow. But getting ahead of this transition is genuinely important. Here's how to start acting today:

1. Spin up RISC-V developer environments now. Platforms like the SiFive HiFive Premier P550 are available and support Red Hat Enterprise Linux. Get your developers building and testing on RISC-V hardware before procurement decisions force the issue.

2. Audit your workloads for RISC-V suitability. AI inference pipelines, edge compute workloads, networking functions, and storage controllers are natural early candidates. Legacy monolithic applications with deep x86 dependencies are not.

3. Engage with the RVA23 profile specification.

The new clarity around RVA23 has enabled organisations to focus their RISC-V development fully on a single target. Building for RVA23 ensures your software will run across a wide range of compatible hardware

— prioritise this as your software compatibility baseline.

4. Monitor the Qualcomm–Ventana integration closely.

Qualcomm has stated that it believes "the RISC-V instruction set architecture has the potential to advance the frontier on CPU technology, enabling innovation across products."

Their server-class roadmap will be one to watch in 2026 and 2027.

5. Join RISC-V International or a member organisation.

A competitive ecosystem of software has already been ported to RISC-V, supporting data centre stacks for compute, networking, and storage. Operators can leverage the same data centre software providers for adjacent use cases in Edge AI, Automotive, and HPC — streamlining integration and reducing resource cost.

Participation gives you early access to platform specs, working groups, and ecosystem partners.

6. Plan for a parallel architecture strategy. Don't plan to replace x86 outright on a single roadmap cycle. Plan to run mixed architectures — x86 for general-purpose and legacy, RISC-V for AI acceleration and greenfield cloud-native workloads — and allow natural migration over time.

7. Track the NVIDIA CUDA-on-RISC-V initiative. If CUDA support matures, the GPU ecosystem — the beating heart of modern AI infrastructure — could land on RISC-V hardware, which would be a transformational unlock.

Conclusion: Not a Revolution Yet, But a Trajectory You Can't Ignore

RISC-V will not replace x86 in the data centre this year, or even next year.

RISC-V's real achievement is not simply technical maturity, but proof that an instruction set can be governed in the open, evolve collaboratively, and still meet the demands of the most exacting commercial and national-scale deployments.

That is a foundation, not a ceiling.

The ARM-in-servers story took over a decade to mature from bold idea to AWS Graviton dominance. RISC-V is on a similar trajectory — but with better timing, stronger ecosystem momentum, and a world increasingly hungry for open, customisable, sovereign compute infrastructure.

People no longer see RISC-V as just an academic project or a simple embedded controller. The open architecture has clearly matured, supported by standard specs, strong corporate support, and a large software ecosystem, and is now ready for applications ranging from enterprise computing and edge AI to the most demanding environments.

The data centre leaders who will win the next decade are the ones doing their homework on RISC-V now. Start your evaluation today — explore RISC-V developer hardware, audit your AI and cloud-native workloads for architectural fit, and build your team's expertise before your competitors do. The open compute era isn't coming. It's already here.