The AI arms race isn't just being fought in the GPU data center anymore. It's now happening inside the CPU itself — and a landmark joint initiative from two longtime rivals is about to change the game for enterprise infrastructure teams everywhere.

Since autumn 2024, AMD and Intel have been cooperating in the x86 Ecosystem Advisory Group (EAG), a consortium designed to coordinate the future evolution of the x86 instruction set architecture in the face of growing competitive pressure from Arm and RISC-V.

The most significant output of that collaboration is now public: the AI Compute Extensions, or ACE — a standardized set of CPU instructions purpose-built for AI and machine learning workloads.

If you're responsible for enterprise infrastructure planning, AI deployment strategy, or server procurement, ACE is something you need to understand now, even if the chips themselves are still a few years away.

What Is ACE, and Why Does It Exist?

ACE represents the first major fruits of the x86 Ecosystem Advisory Group, delivering a new set of matrix instructions that the two companies claim produce a massive AI performance leap over current instructions like Advanced Vector Extensions (AVX). ACE aims to unify AI workloads on x86 CPUs, enhancing energy efficiency and software compatibility so applications will run without breaking across both x86 platforms.

In plain terms, today's x86 CPUs aren't well-suited for the matrix math that powers AI.

Matrix multiplication is a core math operation in AI where two grids of numbers are combined to produce a new grid. In AI, it's the main way neural networks transform inputs into outputs, showing up throughout training and inference in deep learning models.

Current SIMD extensions, such as AVX used by both Intel and AMD, can perform matrix multiplication, but their math throughput is nowhere near that of GPUs, which are built for it.

ACE is designed to close that gap — not by replacing GPUs, but by making the CPU a much more capable co-processor for AI tasks.

How ACE Actually Works: The Technical Picture

ACE's core innovation lies in how it handles 2D computation.

Traditional vectorized hardware (SIMD) instructions like AVX operate on one-dimensional data. Machine learning, powered by Matrix Multiplication and Accumulate (MMA), has created a demand for specialized hardware that runs in two dimensions — a need that led to the rise of Tensor Cores in GPUs. ACE now brings that same logic to the x86 CPU.

ACE uses an outer-product algorithm and eight new 2D Tile Registers, each with 16×16 dimensions and 32-bit precision. Large AI datasets are split into sub-matrices, with the hardware consuming two 16×4 input matrices at 8-bit precision.

The performance uplift is dramatic.

Intel and AMD have jointly developed the AI Compute Extensions (ACE) for x86 CPUs, boosting AI compute density 16 times over AVX10 by using 2D tile registers and outer-product algorithms.

Critically, ACE isn't a radical architectural departure.

ACE integrates seamlessly with AVX10, providing a low-friction and ubiquitous matrix acceleration capability for the x86 ecosystem.

The design suggests these new registers will be implemented within the processor core using the same physical register file used for 512-bit ZMM registers from AVX-512/AVX10 — allowing efficient reuse of existing infrastructure and transistors.

ACE also embraces modern AI data formats.

In line with its AI-focused design, ACE supports various reduced-precision numerical formats including 8-bit integer INT8, 8-bit floating-point formats OCP FPM8, OCP MXFP8, and MXINT8, as well as 16-bit formats

— all common requirements for quantized model inference.

Why a Joint Standard Matters More Than the Tech Itself

One of the most consequential aspects of ACE isn't the raw performance boost — it's the fact that both Intel and AMD are committed to the same spec. Enterprise IT teams will remember the chaos of AVX-512.

This standardisation prevents excessive fragmentation within the x86 CPU market, directly avoiding the problems that faced the AVX-512 instruction set and its many variations.

ACE instructions will have support from both AMD and Intel, giving software developers a strong incentive to use them. These aren't instructions specific to CPUs from a single vendor, and CPU makers are unlikely to abandon these instructions with future product generations. If these new instructions can accelerate workloads, software vendors have no reason not to support them.

It also allows reuse of existing AVX10 optimizations, crafting a scalable matrix acceleration framework for a wide range of implementations, from laptops to supercomputers.

That cross-platform scalability matters enormously for enterprises managing diverse hardware fleets.

The x86 vs. ARM Competitive Context

To fully understand ACE, you need to appreciate the competitive pressure that produced it.

The AI boom has put pressure on every chip architecture. GPUs dominate large-scale AI training and inference, while Arm and custom accelerators are growing in importance across data centers, laptops, phones, and edge devices.

Competitor ARM has already specified Scalable Matrix Extensions (SME2), which build on the Scalable Vector Extensions (SVE2), with SME compute units integrable into ARM SoCs in various ways.

Apple has been incorporating SME2 since the M4, and Qualcomm since the Snapdragon X2.

ACE is x86's answer to that challenge.

The EAG was established in 2024 to blunt the increasing competitiveness of the ARM architecture in the desktop and server environment, with the goal of ending fragmentation between the two x86 architectures — and in that regard, this move succeeds. Even though Intel and AMD both make x86 chips, there has been some fragmentation and incompatibility between the two lines, making this cooperation a very positive sign.

For enterprises heavily invested in x86 infrastructure, this is reassuring news.

The main challenge for ARM revolves around software compatibility and the entrenched ecosystem supporting x86 applications. Many enterprise and legacy programs, particularly in finance, design, and engineering, are still optimized for x86 instruction sets.

ACE strengthens x86's hand without requiring enterprises to abandon their existing stacks.

What ACE Means Specifically for Enterprise Infrastructure

The enterprise implications of ACE span several dimensions: server workloads, edge deployments, and total cost of ownership.

Server-Side AI Support Tasks

In servers, ACE could help CPUs handle AI support tasks more efficiently, even when GPUs or accelerators are doing the heaviest work. CPUs still manage data movement, preprocessing, scheduling, and many mixed workloads

— and doing all of that more efficiently translates directly into throughput gains and cost savings.

Edge and GPU-Less Environments

While ACE closes the gap between CPU and GPU for both inference and training, it still doesn't make the CPU truly competitive with the GPU, according to Jim McGregor, principal analyst with TIRIAS Research. "The CPU will never be more efficient than the GPU/AI accelerator," he said. "However, it does allow you to offload some AI workloads to the CPU and/or use the CPU for AI workloads in applications that may not have a GPU or AI accelerator, such as embedded/edge applications."

Latency-Sensitive Inference

Most AI model inference involves a GPU of some sort, but not every AI task is suited to that hardware. Smaller models or single-user, latency-sensitive operations can benefit from running on the CPU instead, as it avoids the overhead of shuffling data to and from the GPU. There are also many situations where there is no GPU available to begin with, or it's a limited integrated affair.

When Will ACE Arrive? The Roadmap Reality

Enterprise planners need to set expectations carefully here.

According to current information, ACE-v1-compatible x86 processors are unlikely to appear before 2028. Neither AMD for Zen 6 nor Intel for Nova Lake has mentioned ACE yet. AMD only mentions a new "Matrix Engine" for Zen 7, presumably ACE-compatible.

Industry analyst McGregor noted, "I'm pleased to see the partnership between the two companies finally paying off. As expected, changes to the instruction set can take a generation or two to filter through the product lines of both companies." The two firms have not announced any product, and there are no indications of when they will release products with ACE imminently.

Software tooling is beginning to be laid though.

Initial software enablement is underway, including integration with compilers, debuggers, and profilers.

Practical Tips for Enterprise Infrastructure Teams

Given the ACE timeline and significance, here's what you should be doing right now:

ACE-v1-compatible x86 processors are unlikely to appear before 2028.

Factor this into multi-year infrastructure roadmaps and avoid over-investing in GPU capacity for CPU-addressable tasks in the interim.

ACE integrates seamlessly with AVX10,

optimizing your software stack for AVX10 now will create a natural upgrade path to ACE without rearchitecting pipelines.

The ACE Specification version 1.15 is available for download on the website of the x86 Ecosystem Advisory Group.

Subscribe to updates and involve your application teams in evaluating the spec early.

If these new instructions can accelerate workloads, software vendors have no reason not to support them

— and you should expect it in future versions.

Conclusion: A Pivotal Moment for x86's AI Future

ACE represents one of the most significant cooperative technical achievements in x86's history.

As AI moves from experimental pilots to production-scale deployment, enterprises are discovering that their existing computing infrastructure is increasingly unfit for purpose. The shift is being driven by the growing cost, scalability, and latency challenges of AI inference, prompting organizations to fundamentally rethink where and how AI workloads should run.

ACE doesn't solve every problem — GPUs will remain dominant for large-scale training and heavy inference workloads. But for enterprise IT leaders managing sprawling, heterogeneous infrastructure, a future where the CPU handles lightweight AI tasks natively, efficiently, and consistently across all x86 hardware is transformative.

AMD and Intel continue to cooperate on the future roadmap for ACE and AVX10, aiming to embrace new opportunities in AI and other workload domains. The widespread adoption and high performance of x86 make it an ideal choice for developers, and the addition of ACE to the ISA further strengthens the future of the x86 ecosystem.

Is your enterprise infrastructure strategy ready for AI-native CPUs? Now is the time to start planning — review your server refresh cycles, engage your vendors on ACE compatibility, and ensure your AI workload architecture is designed to exploit the performance gains coming down the x86 pipeline. The organizations that plan ahead will be the ones who gain the most when ACE-compatible processors finally arrive.